LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY synth;
USE synth.vhdlsynth.all;

ENTITY TOP IS
END TOP;

ARCHITECTURE TOP_ARCH OF TOP IS

SIGNAL clk,
       load,
       ready      : STD_LOGIC := '0';
SIGNAL in_data_1,
       in_data_2  : STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000";
SIGNAL out_data   : STD_LOGIC_VECTOR (15 DOWNTO 0) := "0000000000000000";

COMPONENT multiplier
PORT (
     clk       : IN STD_LOGIC;                       -- Takt
     load      : IN STD_LOGIC;                       -- "Werte laden" Signal
     in_data_1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);    -- 1. Faktor
     in_data_2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);    -- 2. Faktor
     ready     : OUT STD_LOGIC;                      -- =1, wenn multiplier fertig ist
     out_data  : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)   -- Ergebnis
     );
END COMPONENT;

FOR TEIL_1: multiplier USE ENTITY WORK.multiplier(multiplier_arch);

COMPONENT testbench
PORT (
     in_data_1,
     in_data_2  : OUT STD_LOGIC_VECTOR(7 downto 0);  -- die beiden Faktoren
     load       : OUT STD_LOGIC;                     -- "Werte Laden" Signal
     ready      : IN STD_LOGIC;                      -- =1, wenn multiplier fertig ist
     clk        : OUT STD_LOGIC                      -- generiertes Taktsignal
     );    
END COMPONENT;

FOR TEIL_2: testbench USE ENTITY WORK.testbench(testbench_arch);

BEGIN
    TEIL_1:  multiplier PORT MAP (clk, load, in_data_1, in_data_2, ready, out_data);
    TEIL_2:  testbench PORT MAP (in_data_1, in_data_2, load, ready, clk);
END TOP_ARCH;